module uart_send 
(
	input 	   		clk		     ,
	input		   		rstn		     ,
	
	input      [7:0]  key		     ,
	input             uart_flag     ,
	output     reg    uart_en       ,
	output reg [7:0]  uart_txd   
	
);

 /* 
parameter CLK_RED = 50_000_000;
parameter UART_BPS = 9600;

localparam BPS_CNT = CLK_RED / (UART_BPS * 16);
*/
reg     uart_en_t0;
reg     uart_en_t1;
wire    en_flag;
reg     presult;

parameter paritymode = 1'b0;

assign en_flag = (~uart_en_t1) & uart_en_t0;

always@(posedge clk or negedge rstn) begin
      if(!rstn) begin 
		   uart_en_t0 <= 1'b0;
         uart_en_t1 <= 1'b0;
		end	
		else begin
		   uart_en_t0 <= uart_flag;
			uart_en_t1 <= uart_en_t0;
			end 
end

reg [15:0] 			clk_cnt ;
reg  [3:0] 			tx_cnt  ;
reg  [7:0] 			tx_data ;
reg               tx_flag ;

always@(posedge clk or negedge rstn)begin
	   if(!rstn) begin 
		   tx_flag <= 1'b1;
			tx_data <= 8'd0;
			end 
	   else if(en_flag) begin
		   tx_flag <= 1'b1;
			tx_data <= key[7:0];
			end     
		else 
		if((tx_cnt == 4'd9) && (clk_cnt <168)) begin
		   tx_flag <= 1'b0;
			tx_data <=8'd0;
         end
      else begin
         tx_flag <= tx_flag;
			tx_data <= tx_data;
   		end
end 
	
always @(posedge clk or negedge rstn)begin

       if(!rstn) begin 
		   tx_cnt  <= 4'd0;
		   //clk_cnt <= 16'd0;
			end 
	    else  if(tx_flag)begin
			     if(clk_cnt < 162)begin
				     //clk_cnt <= clk_cnt + 1'b1;
					  tx_cnt  <= tx_cnt;
					  end 
				  else begin
				   //  clk_cnt <= 16'd0;
					  tx_cnt  <= tx_cnt + 1'b1;
					  end 
		 end 
		 else begin
		   tx_cnt  <= 4'd0;
		  // clk_cnt <= 16'd0;
			end
end 
always @(posedge clk or negedge rstn)
begin
if (!rstn) begin
uart_txd <= 1'b0;
uart_en <= 1'b0;
clk_cnt<=8'd0;
presult<=1'b0;
end
else if(tx_flag == 1'b1) begin
case(clk_cnt) //产生起始位
8'd0: begin
uart_txd <= 1'b0;
uart_en <= 1'b1;
clk_cnt <= clk_cnt + 8'd1;
end
8'd16: begin
uart_txd <= key[0]; //发送数据 0 位
presult <= key[0]^paritymode;
uart_en <= 1'b1;
clk_cnt <= clk_cnt + 8'd1;
end
8'd32: begin

uart_txd <= key[1]; //发送数据 1 位
presult <= key[1]^presult;
uart_en <= 1'b1;
clk_cnt <= clk_cnt + 8'd1;
end
8'd48: begin
uart_txd <= key[2]; //发送数据 2 位
presult <= key[2]^presult;
uart_en <= 1'b1;
clk_cnt <= clk_cnt + 8'd1;
end
8'd64: begin
uart_txd <= key[3]; //发送数据 3 位
presult <= key[3]^presult;
uart_en <= 1'b1;
clk_cnt <= clk_cnt + 8'd1;
end
8'd80: begin
uart_txd <= key[4]; //发送数据 4 位
presult <= key[4]^presult;
uart_en <= 1'b1;
clk_cnt <= clk_cnt + 8'd1;
end
8'd96: begin
uart_txd <= key[5]; //发送数据 5 位
presult <=key[5]^presult;
uart_en <= 1'b1;
clk_cnt <= clk_cnt + 8'd1;
end
8'd112: begin
uart_txd <= key[6]; //发送数据 6 位
presult <= key[6]^presult;
uart_en<= 1'b1;
clk_cnt <= clk_cnt + 8'd1;
end
8'd128: begin
uart_txd <= key[7]; //发送数据 7 位
presult <= key[7]^presult;
uart_en <= 1'b1;
clk_cnt <= clk_cnt + 8'd1;
end
8'd144: begin
uart_txd <= presult; //发送奇偶校验位
presult <= key[0]^paritymode;
uart_en <= 1'b1;
clk_cnt <= clk_cnt + 8'd1;
end
8'd160: begin
uart_txd <= 1'b1; //发送停止位
uart_en <= 1'b1;
clk_cnt <= clk_cnt + 8'd1;
end
8'd168: begin
uart_txd <= 1'b1;
uart_en <= 1'b0; //一帧数据发送结束
clk_cnt <= clk_cnt + 8'd1;
end
default: begin
clk_cnt <= clk_cnt + 8'd1;
end
endcase
end
else begin
uart_txd <= 1'b1;
clk_cnt <= 8'd0;
uart_en <= 1'b0;
end
end
endmodule 
/*
always@(posedge clk or negedge rstn)begin
      if(!rstn)
	      uart_txd <= 1'b1;
		else if(tx_flag) begin
	      case(tx_cnt)
				  4'd0: uart_txd<=1'b0; //起始位 应该是低电平
	           4'd1: uart_txd<=tx_data[0];
				  4'd2: uart_txd<=tx_data[1];
				  4'd3: uart_txd<=tx_data[2];
	           4'd4: uart_txd<=tx_data[3];
	           4'd5: uart_txd<=tx_data[4];
	           4'd6: uart_txd<=tx_data[5];
	           4'd7: uart_txd<=tx_data[6];
	           4'd8: uart_txd<=tx_data[7];//从低到高依次放在数据线上输出
				  4'd9: uart_txd<=1'b1; //停止位
	  default:;
	  endcase
	  end 
else uart_txd <= 1'b1;
end 
endmodule
	*/	  
					  
			  
			
			
			








































		